As DRAMs increase in memory cell density, there is a continuing challenge to maintain a sufficiently high storage capacitance despite decreasing cell area. A principal way of increasing cell density is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors.
With a conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Example capacitor constructions are shown by T. Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M And 64M DRAMs", IEDM Tech Digest, pp. 592-595, 1988; S. Inoue et al. "A Spread Stack Capacitor (SSC) Cell For 64M Bit DRAMS", IEDM Tech Digest, pp. 31-34, 1989; and U.S. Pat. No. 5,061,650 to Dennison et al. and references cited therein.
It would be desirable to improve upon these and other processes in providing three dimensional stacked capacitors which maximize capacitance.